| Summary: | As integrated circuits become more and more complex, the ability to make post fabrication
changes will become more and more attractive. This ability can be realized using
programmable logic cores. Currendy, such cores are available from vendors in the form of a
"hard" layout. In this thesis, we focus on an alternative approach: vendors supply a
synthesizable version of their programmable logic core (a "soft" core) and the integrated
circuit designer synthesizes the programmable logic fabric using standard cells. Although this
technique suffers increased speed, density and power overhead, the task of integrating such
cores is far easier than integrating "hard" cores into an ASIC. For very small amounts of logic,
this ease of use may be more important than the increased overhead. This thesis presents three
synthesizable programmable logic core architectures. The place and route algorithms
developed for the various architectures are also described. These algorithms have been
integrated in the Versatile Place and Route (VPR) CAD tool, a widely used CAD tool for FPGA
architectural studies. We compare the architectures to each other, and to a "hard"
programmable logic core. We also show how these cores can be made more efficient by
creating a non-rectangular architecture, an option not available to "hard" core vendors. Finally,
we evaluate various approaches to improve the area performance of our architectures by
considering several architectural enhancements.
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