JTAG sąsaja programuojamuose elektroniniuose prietaisuose
This master‘s final paper describes JTAG (boundary scan) interface in which discuss IEEE standart 1149.1 circuit model and the main TAP (Test Access Port) controllers instructions. Accomplished programmable integral logical ICs overview: development, leading manufacturer (ALTERA, XILINX, ACTEL) prod...
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| Format: | Dissertation |
| Language: | Lithuanian |
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Lithuanian Academic Libraries Network (LABT)
2005
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| Online Access: | http://vddb.library.lt/fedora/get/LT-eLABa-0001:E.02~2005~D_20050615_150741-49753/DS.005.0.01.ETD |