Architecture Descriptions for Retargetable Code Translation

The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level de...

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Bibliographic Details
Main Author: Ravindra, D V
Other Authors: Srikant, Y N
Format: Others
Language:en
Published: Indian Institute of Science 2005
Subjects:
Online Access:http://hdl.handle.net/2005/88
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spelling ndltd-IISc-oai-etd.ncsi.iisc.ernet.in-2005-882013-01-07T21:20:05ZArchitecture Descriptions for Retargetable Code TranslationRavindra, D VComputer and Information ScienceArchitecture DescriptionAutomatic Code GenerationBasic NotationCode GeneratorThe study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level descriptions to aid code selection and storage allocation. The view taken in the thesis is that a description specializes a framework with a particular architecture. Independently, the framework must support other translation algorithms without constraining their freedom or forcing them towards architecture-specific idioms. The first contribution is an architectural description language with features tuned towards better parameterizability. Emphasis is laid on addressing site (compile time) parameterizability. Within the notation, the type system of the machine is decoupled from that of the language with the mapping being left to the user as a compile-time parameterization. This gives one more degree of freedom for the user to decide on the precision required based on the available realizations. We also give adequate representation to addressing modes. They are considered to be almost equivalent to operations in complexity. This makes the specification simpler for operations. From the framework's perspective, as a second contribution, we propose an algorithm for maintaining registers during allocation. Register allocation algorithms depend on the framework to inform them when registers are exhausted. In such a situation, we pro- pose an adaptation of bipartite graph matching to keep track of register usage during translation in the presence of architec- tural constraints. The research also aims at structuring both the specification and software to prevent the closed-syntax bottle- neck of a lot of specification languages. We also describe the architecture of the implementation in terms of a very flexible model called the blackboard model.Indian Institute of ScienceSrikant, Y N2005-03-14T10:50:25Z2005-03-14T10:50:25Z2005-03-14T10:50:25Z2000-04Electronic Thesis and Dissertation1123685 bytesapplication/pdfhttp://hdl.handle.net/2005/88nullenI grant Indian Institute of Science the right to archive and to make available my thesis or dissertation in whole or in part in all forms of media, now hereafter known. I retain all proprietary rights, such as patent rights. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.
collection NDLTD
language en
format Others
sources NDLTD
topic Computer and Information Science
Architecture Description
Automatic Code Generation
Basic Notation
Code Generator
spellingShingle Computer and Information Science
Architecture Description
Automatic Code Generation
Basic Notation
Code Generator
Ravindra, D V
Architecture Descriptions for Retargetable Code Translation
description The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level descriptions to aid code selection and storage allocation. The view taken in the thesis is that a description specializes a framework with a particular architecture. Independently, the framework must support other translation algorithms without constraining their freedom or forcing them towards architecture-specific idioms. The first contribution is an architectural description language with features tuned towards better parameterizability. Emphasis is laid on addressing site (compile time) parameterizability. Within the notation, the type system of the machine is decoupled from that of the language with the mapping being left to the user as a compile-time parameterization. This gives one more degree of freedom for the user to decide on the precision required based on the available realizations. We also give adequate representation to addressing modes. They are considered to be almost equivalent to operations in complexity. This makes the specification simpler for operations. From the framework's perspective, as a second contribution, we propose an algorithm for maintaining registers during allocation. Register allocation algorithms depend on the framework to inform them when registers are exhausted. In such a situation, we pro- pose an adaptation of bipartite graph matching to keep track of register usage during translation in the presence of architec- tural constraints. The research also aims at structuring both the specification and software to prevent the closed-syntax bottle- neck of a lot of specification languages. We also describe the architecture of the implementation in terms of a very flexible model called the blackboard model.
author2 Srikant, Y N
author_facet Srikant, Y N
Ravindra, D V
author Ravindra, D V
author_sort Ravindra, D V
title Architecture Descriptions for Retargetable Code Translation
title_short Architecture Descriptions for Retargetable Code Translation
title_full Architecture Descriptions for Retargetable Code Translation
title_fullStr Architecture Descriptions for Retargetable Code Translation
title_full_unstemmed Architecture Descriptions for Retargetable Code Translation
title_sort architecture descriptions for retargetable code translation
publisher Indian Institute of Science
publishDate 2005
url http://hdl.handle.net/2005/88
work_keys_str_mv AT ravindradv architecturedescriptionsforretargetablecodetranslation
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