Architecture Descriptions for Retargetable Code Translation

The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level de...

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Bibliographic Details
Main Author: Ravindra, D V
Other Authors: Srikant, Y N
Format: Others
Language:en
Published: Indian Institute of Science 2005
Subjects:
Online Access:http://hdl.handle.net/2005/88
Description
Summary:The study of architectural parameterization has long neglected other parameterizations in favour of code selector descriptions. In this dissertation, we are concerned with providing linguistic notations for modelling architectures with special emphasis on translation. We focus on high level descriptions to aid code selection and storage allocation. The view taken in the thesis is that a description specializes a framework with a particular architecture. Independently, the framework must support other translation algorithms without constraining their freedom or forcing them towards architecture-specific idioms. The first contribution is an architectural description language with features tuned towards better parameterizability. Emphasis is laid on addressing site (compile time) parameterizability. Within the notation, the type system of the machine is decoupled from that of the language with the mapping being left to the user as a compile-time parameterization. This gives one more degree of freedom for the user to decide on the precision required based on the available realizations. We also give adequate representation to addressing modes. They are considered to be almost equivalent to operations in complexity. This makes the specification simpler for operations. From the framework's perspective, as a second contribution, we propose an algorithm for maintaining registers during allocation. Register allocation algorithms depend on the framework to inform them when registers are exhausted. In such a situation, we pro- pose an adaptation of bipartite graph matching to keep track of register usage during translation in the presence of architec- tural constraints. The research also aims at structuring both the specification and software to prevent the closed-syntax bottle- neck of a lot of specification languages. We also describe the architecture of the implementation in terms of a very flexible model called the blackboard model.