Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

Bibliographic Details
Main Author:	Valluri, Madhavi Gopal
Other Authors:	Govindarajan, R
Language:	en_US
Published:	2011
Subjects:	Compiling (Electronic Computers) Multiprocessors Instruction Scheduling Compilers Register Allocation Machine Models Instruction-Level Parallelism (ILP) Very Long Instruction Word (VLIW) Processors Modulo-Variable Expansion (MVE) Sensitive Scheduling Computer Science
Online Access:	http://etd.iisc.ernet.in/handle/2005/1532 http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdf

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