Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors

Bibliographic Details
Main Author: Valluri, Madhavi Gopal
Other Authors: Govindarajan, R
Language:en_US
Published: 2011
Subjects:
Compiling (Electronic Computers)
Multiprocessors
Instruction Scheduling
Compilers
Register Allocation
Machine Models
Instruction-Level Parallelism (ILP)
Very Long Instruction Word (VLIW) Processors
Modulo-Variable Expansion (MVE)
Sensitive Scheduling
Computer Science
Online Access:http://etd.iisc.ernet.in/handle/2005/1532
http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdf
id ndltd-IISc-oai-etd.ncsi.iisc.ernet.in-2005-1532
record_format oai_dc
spelling ndltd-IISc-oai-etd.ncsi.iisc.ernet.in-2005-15322018-01-10T03:35:59ZEvaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue ProcessorsValluri, Madhavi GopalCompiling (Electronic Computers)MultiprocessorsInstruction SchedulingCompilersRegister AllocationMachine ModelsInstruction-Level Parallelism (ILP)Very Long Instruction Word (VLIW) ProcessorsModulo-Variable Expansion (MVE)Sensitive SchedulingComputer ScienceGovindarajan, R2011-11-16T05:13:48Z2011-11-16T05:13:48Z2011-11-161999-01Thesishttp://etd.iisc.ernet.in/handle/2005/1532http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdfen_USG23229
collection NDLTD
language en_US
sources NDLTD
topic Compiling (Electronic Computers)
Multiprocessors
Instruction Scheduling
Compilers
Register Allocation
Machine Models
Instruction-Level Parallelism (ILP)
Very Long Instruction Word (VLIW) Processors
Modulo-Variable Expansion (MVE)
Sensitive Scheduling
Computer Science
spellingShingle Compiling (Electronic Computers)
Multiprocessors
Instruction Scheduling
Compilers
Register Allocation
Machine Models
Instruction-Level Parallelism (ILP)
Very Long Instruction Word (VLIW) Processors
Modulo-Variable Expansion (MVE)
Sensitive Scheduling
Computer Science
Valluri, Madhavi Gopal
Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
author2 Govindarajan, R
author_facet Govindarajan, R
Valluri, Madhavi Gopal
author Valluri, Madhavi Gopal
author_sort Valluri, Madhavi Gopal
title Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
title_short Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
title_full Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
title_fullStr Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
title_full_unstemmed Evaluation Of Register Allocation And Instruction Scheduling Methods In Multiple Issue Processors
title_sort evaluation of register allocation and instruction scheduling methods in multiple issue processors
publishDate 2011
url http://etd.iisc.ernet.in/handle/2005/1532
http://etd.ncsi.iisc.ernet.in/abstracts/1959/G15406-Abs.pdf
work_keys_str_mv AT vallurimadhavigopal evaluationofregisterallocationandinstructionschedulingmethodsinmultipleissueprocessors
_version_ 1718603458453438464

Similar Items