Proposal of two solutions to cope with the faulty behavior of circuits in future technologies

Proposal of two solutions to cope with the faulty behavior of circuits in future technologies

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A diminuição no tamanho dos dispositivos nas tecnologias do futuro traz consigo um grande aumento na taxa de erros dos circuitos, na lógica combinacional e seqüencial. Apesar de algumas potenciais soluções começarem a ser investigadas pela comunidade, a busca por circuitos tolerantes a erros induzid...

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Bibliographic Details
Main Author: Rhod, Eduardo Luis
Other Authors: Carro, Luigi
Format: Others
Language:English
Published: 2009
Subjects:
Microeletrônica
Tolerância a falhas
Fault tolerant architectures
Memory based architectures
Reliable SoCs
Error detection techniques
Soft error rate
Online Access:http://hdl.handle.net/10183/16086
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