Contribuições para o problema de verificação de equivalência combinacional
=== A decrease the SAT solver solving time used to prove equivalence between the circuits. Through this technique, which was implemented in a tool called Vimplic, we have been able to dramatically reduce the overall verification time of several circuits outperforming the state-of-the-art techniques...
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| Format: | Others |
| Language: | Portuguese |
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Universidade Federal de Minas Gerais
2008
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| Online Access: | http://hdl.handle.net/1843/RVMR-7K6R63 |