Um verificador de modelos explícito-simbólico
=== In this work we propose a modeling that combines explicit and symbolic representations in an explicit-symbolic formal verification model. Both explicit and symbolic models have been successfully used in the verification of finite state concurrent systems, such as complex sequential circuits and...
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| Format: | Others |
| Language: | Portuguese |
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Universidade Federal de Minas Gerais
2005
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| Online Access: | http://hdl.handle.net/1843/RVMR-6EAPMC |