Modeling and Analysis of High-Frequency Microprocessor Clocking Networks

Modeling and Analysis of High-Frequency Microprocessor Clocking Networks

Integrated systems with billions of transistors on a single chip are a now reality. These systems include multi-core microprocessors and are built today using deca-nanometer devices organized into synchronous digital circuits. The movement of data within such systems is regulated by a set of predict...

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Bibliographic Details
Main Author: Saint-Laurent, Martin
Format: Others
Language:en_US
Published: Georgia Institute of Technology 2005
Subjects:
Phase-locked loops
Interlevel coupling noise
Power-performance tradeoff
Skew compensation
Interconnect
Power supply noise
Skew
Clock distribution
Low-power design
Jitter
MOSFET model
Timing circuits Design and construction
Metal oxide semiconductor field-effect transistors
Low voltage integrated circuits Design and construction
Interconnects (Integrated circuit technology)
Online Access:http://hdl.handle.net/1853/7271

Internet

http://hdl.handle.net/1853/7271

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