Interconnects for future technology generations - conventional CMOS with copper/low-k and beyond
The limitations of the conventional Cu/low-k interconnect technology for use in future ultra-scaled integrated circuits down to 7 nm in the year 2020 are investigated from the power/performance point of view. Compact models are used to demonstrate the impacts of various interconnect process paramete...
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| Format: | Others |
| Language: | en_US |
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Georgia Institute of Technology
2015
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| Online Access: | http://hdl.handle.net/1853/53080 |