MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array

MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array

Bibliographic Details
Main Author:	Owen, Henry L., III
Format:	Others
Language:	en_US
Published:	Georgia Institute of Technology 2007
Subjects:	Computer-aided design Engineering mathematics
Online Access:	http://hdl.handle.net/1853/13549

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