Hardware/Software Co-Verification Using the SystemVerilog DPI

• Main Author: Freitas, Arthur
• Other Authors: Hardt, Wolfram
• Language: English
• Published: Technische Universität Chemnitz 2007
• Subjects: info:eu-repo/classification/ddc/004; ddc:004; info:eu-repo/classification/ddc/500; ddc:500; Systementwurf; Verifikation; Hardware/Software-Co simulation; Hyperstone S5 Flash memory controller; System Verilog direct programming interface; logic simulation
• Online Access: http://nbn-resolving.de/urn:nbn:de:swb:ch1-200700941; https://monarch.qucosa.de/id/qucosa%3A18736; https://monarch.qucosa.de/api/qucosa%3A18736/attachment/ATT-0/; https://monarch.qucosa.de/api/qucosa%3A18736/attachment/ATT-1/

During the design and verification of the Hyperstone S5 flash memory controller, we developed a highly effective way to use the SystemVerilog direct programming interface (DPI) to integrate an instruction set simulator (ISS) and a software debugger in logic simulation. The processor simulation was performed by the ISS, while all other hardware components were simulated in the logic simulator. The ISS integration allowed us to filter many of the bus accesses out of the logic simulation, accelerating runtime drastically. The software debugger integration freed both hardware and software engineers to work in their chosen development environments. Other benefits of this approach include testing and integrating code earlier in the design cycle and more easily reproducing, in simulation, problems found in FPGA prototypes.