Design, implementation and prototyping of an iterative receiver for bit-interleaved coded modulation system dedicated to DVB-T2

• Main Author: Li, Meng
• Language: ENG
• Published: 2012
• Subjects: [SPI:SIGNAL] Engineering Sciences/Signal and Image processing; [INFO:INFO_TS] Computer Science/Signal and Image Processing; DVB-T2 standard; signal-space diversity; rotated QAM; 2D Demapper; LDPC decoder; iterative receiver; turbo-demodulation; FPGA; prototype
• Online Access: http://tel.archives-ouvertes.fr/tel-00719312; http://tel.archives-ouvertes.fr/docs/00/71/93/12/PDF/2012telb0225_Li_Meng.pdf

In 2008, the European Digital Video Broadcasting (DVB) standardization committee issued the second generation of Digital Video Broadcasting-Terrestrial (DVB-T2) standard in order to enable the wide broadcasting of high definition and 3D TV programmes. DVB-T2 has adopted several new technologies to provide more robust reception compared to the first genaration standard. One important technology is the bit interleaved coded modulation (BICM) with doubled signal space diversity plus the usage of low-density parity check (LDPC) codes. Both techniques can be combined at the receiver side through an iterative process between the decoder and demapper in order to further increase the system performance. The object of my study was to design and prototype a DVB-T2 receiver which supports iterative process. The two main contributions to the demapper design are the proposal of a linear approximation of Euclidean distance computation and the derivation of a sub-region detection algorithm for the two-dimensional demapper. Both contributions allows the computational complexity of the demapper to be reduced for its hardware implementation. In order to enable iterative processing between the demapper and the decoder, we investigated the use of vertical shuffled Min-Sum LDPC decoding algorithm. A novel vertical shuffled iterative structure aiming at reducing the latency of iterative processing and the corresponding architecture of the decoder were proposed. The proposed demapper and decoder have been integrated in a real DVB-T2 demodulator and tested in order to validate the efficiency of the proposed architecture. The prototype of a simplified DVB-T2 transceiver has been implemented, in which the receiver supports both non-iterative process and iterative process. We published the first paper related to a DVB-T2 iterative receiver.