REST: A Leaf Cell Design System
This thesis describes a leaf cell design system, REST, Richard's Editor for Sticks. REST is intended to be used for the preparation of the lowest level cells in an integrated circuit design. A stick notation is used in the editing process. Given a structured design methodology any design task c...
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| Format: | Others |
| Language: | en |
| Published: |
1981
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| Online Access: | https://thesis.library.caltech.edu/6927/1/Mosteller_rc_1981.pdf Mosteller, R. C. (1981) REST: A Leaf Cell Design System. Master's thesis, California Institute of Technology. doi:10.7907/1r9d-ad60. https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185 <https://resolver.caltech.edu/CaltechTHESIS:04122012-162654185> |
| Summary: | This thesis describes a leaf cell design system, REST, Richard's Editor for Sticks. REST is intended to be used for the preparation of the lowest level cells in an integrated circuit design. A stick notation is used in the editing process. Given a structured design methodology any design task can be separated into two parts: 1) leaf cell design and 2) composition cell design. This tool addresses the first of these tasks, although it may also be used for general manipulation of stick diagrams. A table driven compaction algorithm is presented. This graph based algorithm uses a weighted affinity factor to reduce total polysilicon and diffusion wire length. A suite of utilities provide functions such as file interface, physical mapping, annotation, etc. consistent with a set of design rules. The system has been implemented in Simula on a DEC 20 computer, and works in conjunction with a limited functional diagramming system. The design rules, models and stick interpretation are table driven and can be changed for various technologies. Currently REST is being used for NMOS technology. A community of users have used the REST system to prepare a number of designs resulting in a substantial reduction of design time. In addition, the system is currently being used at a major computer manufacturer in conjunction with a VLSI design course. |
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