A fault tolerant integrated circuit memory
<p>Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to p...
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| Format: | Others |
| Language: | en |
| Published: |
1980
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| Online Access: | https://thesis.library.caltech.edu/6861/2/Barton_af_1980.pdf Barton, Anthony Francis (1980) A fault tolerant integrated circuit memory. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/dr7k-qn11. https://resolver.caltech.edu/CaltechTHESIS:03212012-110600634 <https://resolver.caltech.edu/CaltechTHESIS:03212012-110600634> |
| Summary: | <p>Most commercially produced integrated circuits are incapable of
tolerating manufacturing defects. The area and function of the
circuits is thus limited by the probability of faults occurring
within the circuit. This thesis examines techniques for using
redundancy in memory circuits to provide fault tolerance and to
increase storage capacity.</p>
<p>A hierarchical memory architecture using multiple Hamming codes
is introduced and analysed to determine its resistance to
manufacturing defects. The results of the analysis indicate that
substantial yield improvement is possible with relatively modest
increases in circuit area. Also, the architecture makes it possible
to build larger memory circuits than is economically feasible
without redundancy.</p> |
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