Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching

Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching

Though the logical correctness of an asynchronous circuit is independent of implementation delays, the cycle time of an asynchronous circuit is of great importance to the designer. Oftentimes, the insertion of buffers to such circuits reduces the cycle time of the circuit without affecting the logi...

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Bibliographic Details
Main Author: Prakash, Piyush
Format: Others
Published: 2008
Online Access:https://thesis.library.caltech.edu/2118/1/thesis.pdf
Prakash, Piyush (2008) Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/9HMY-RR92. https://resolver.caltech.edu/CaltechETD:etd-05262008-234258 <https://resolver.caltech.edu/CaltechETD:etd-05262008-234258>

Internet

https://thesis.library.caltech.edu/2118/1/thesis.pdf
Prakash, Piyush (2008) Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/9HMY-RR92. https://resolver.caltech.edu/CaltechETD:etd-05262008-234258 <https://resolver.caltech.edu/CaltechETD:etd-05262008-234258>

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