A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems
<p>A hierarchical timing simulation model for digital MOS circuits and systems is presented. This model supports the structured design methodology, and can be applied to both "structure" and "behavior" representations of designs in a uniform manner. A simulator based on thi...
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| Format: | Others |
| Language: | en |
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1985
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| Online Access: | https://thesis.library.caltech.edu/1331/1/Lin_tm_1985.pdf Lin, Tzu-mu (1985) A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/41bh-7e43. https://resolver.caltech.edu/CaltechETD:etd-04102008-105646 <https://resolver.caltech.edu/CaltechETD:etd-04102008-105646> |
Internet
https://thesis.library.caltech.edu/1331/1/Lin_tm_1985.pdfLin, Tzu-mu (1985) A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/41bh-7e43. https://resolver.caltech.edu/CaltechETD:etd-04102008-105646 <https://resolver.caltech.edu/CaltechETD:etd-04102008-105646>