Monte Carlo Methods for 2-D Compaction
<p>A new method of compaction for VLSI circuits is presented. Compaction is done simultaneously in two dimensions and uses a Monte Carlo simulation method often referred to as simulated annealing for optimization. A new curvilinear representation for VLSI circuits, specifically chosen to make...
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| Format: | Others |
| Language: | en |
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1986
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| Online Access: | https://thesis.library.caltech.edu/1035/1/Mosteller_rc_1986.pdf Mosteller, Richard Craig (1986) Monte Carlo Methods for 2-D Compaction. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/mwrq-t026. https://resolver.caltech.edu/CaltechETD:etd-03202008-091615 <https://resolver.caltech.edu/CaltechETD:etd-03202008-091615> |