A Parallel Execution Model for Logic Programming

<p>The Sync Model, a parallel execution method for logic programming, is proposed. The Sync Model is a multiple-solution data-driven model that realizes AND-parallelism and OR-parallelism in a logic program assuming a message-passing multiprocessor system. AND parallelism is implemented by con...

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Main Author: Li, Peyyun Peggy
Format: Others
Language:en
Published: 1986
Online Access:https://thesis.library.caltech.edu/1023/1/Li_pp_1986.pdf
Li, Peyyun Peggy (1986) A Parallel Execution Model for Logic Programming. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/2ngs-bp80. https://resolver.caltech.edu/CaltechETD:etd-03192008-143903 <https://resolver.caltech.edu/CaltechETD:etd-03192008-143903>
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spelling ndltd-CALTECH-oai-thesis.library.caltech.edu-10232021-04-17T05:01:34Z https://thesis.library.caltech.edu/1023/ A Parallel Execution Model for Logic Programming Li, Peyyun Peggy <p>The Sync Model, a parallel execution method for logic programming, is proposed. The Sync Model is a multiple-solution data-driven model that realizes AND-parallelism and OR-parallelism in a logic program assuming a message-passing multiprocessor system. AND parallelism is implemented by constructing a dynamic data flow graph of the literals in the clause body with an ordering algorithm. OR parallelism is achieved by adding special Synchronization signals to the stream of partial solutions and synchronizing the multiple streams with a merge algorithm.</p> <p>The Sync Model is proved to be sound and complete. Soundness means it only generates correct solutions and completeness means it generates all the correct solutions. The soundness and completeness of the Sync Model are implied by the correctness of the merge algorithm.</p> <p>A new class of interconnection networks, the Sneptree, is also presented. The Sneptree is an augmented complete binary tree which can simulate an unbounded complete binary tree optimally. Amongst different connection patterns of the Sneptree, some are regular and extensible so as to be well suited for VLSI implementation. A recursive method is presented to generate the H-structure layout of one type of the Sneptree, called the Cyclic Sneptree. A message routing algorithm between any two leaf nodes of the Cyclic Sneptree is also presented. The routing algorithm, which is of O(n) complexity, gives a good approximation to the shortest path.</p> <p>The Sneptree is an ideal architecture for the Sync model, in which a dynamic process tree is constructed. With a simple mapping algorithm, the Sync Model can be mapped onto the Sneptree with highly-balanced load and low overhead.</p> 1986 Thesis NonPeerReviewed application/pdf en other https://thesis.library.caltech.edu/1023/1/Li_pp_1986.pdf Li, Peyyun Peggy (1986) A Parallel Execution Model for Logic Programming. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/2ngs-bp80. https://resolver.caltech.edu/CaltechETD:etd-03192008-143903 <https://resolver.caltech.edu/CaltechETD:etd-03192008-143903> https://resolver.caltech.edu/CaltechETD:etd-03192008-143903 CaltechETD:etd-03192008-143903 10.7907/2ngs-bp80
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description <p>The Sync Model, a parallel execution method for logic programming, is proposed. The Sync Model is a multiple-solution data-driven model that realizes AND-parallelism and OR-parallelism in a logic program assuming a message-passing multiprocessor system. AND parallelism is implemented by constructing a dynamic data flow graph of the literals in the clause body with an ordering algorithm. OR parallelism is achieved by adding special Synchronization signals to the stream of partial solutions and synchronizing the multiple streams with a merge algorithm.</p> <p>The Sync Model is proved to be sound and complete. Soundness means it only generates correct solutions and completeness means it generates all the correct solutions. The soundness and completeness of the Sync Model are implied by the correctness of the merge algorithm.</p> <p>A new class of interconnection networks, the Sneptree, is also presented. The Sneptree is an augmented complete binary tree which can simulate an unbounded complete binary tree optimally. Amongst different connection patterns of the Sneptree, some are regular and extensible so as to be well suited for VLSI implementation. A recursive method is presented to generate the H-structure layout of one type of the Sneptree, called the Cyclic Sneptree. A message routing algorithm between any two leaf nodes of the Cyclic Sneptree is also presented. The routing algorithm, which is of O(n) complexity, gives a good approximation to the shortest path.</p> <p>The Sneptree is an ideal architecture for the Sync model, in which a dynamic process tree is constructed. With a simple mapping algorithm, the Sync Model can be mapped onto the Sneptree with highly-balanced load and low overhead.</p>
author Li, Peyyun Peggy
spellingShingle Li, Peyyun Peggy
A Parallel Execution Model for Logic Programming
author_facet Li, Peyyun Peggy
author_sort Li, Peyyun Peggy
title A Parallel Execution Model for Logic Programming
title_short A Parallel Execution Model for Logic Programming
title_full A Parallel Execution Model for Logic Programming
title_fullStr A Parallel Execution Model for Logic Programming
title_full_unstemmed A Parallel Execution Model for Logic Programming
title_sort parallel execution model for logic programming
publishDate 1986
url https://thesis.library.caltech.edu/1023/1/Li_pp_1986.pdf
Li, Peyyun Peggy (1986) A Parallel Execution Model for Logic Programming. Dissertation (Ph.D.), California Institute of Technology. doi:10.7907/2ngs-bp80. https://resolver.caltech.edu/CaltechETD:etd-03192008-143903 <https://resolver.caltech.edu/CaltechETD:etd-03192008-143903>
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