Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels

This thesis combines Keysight’s SystemVue software with a Vector Signal Analyzer (VSA) and Vector Signal Generator (VSG) to test receiver equalization schemes over physical channels. The testing setup, “Equalization Verification,” is intended to be able to evaluate any equalization scheme over any p...

Full description

Bibliographic Details
Main Authors: Ritter, David M, Smilkstein, Tina, Dr.
Format: Others
Published: DigitalCommons@CalPoly 2017
Subjects:
Online Access:https://digitalcommons.calpoly.edu/theses/1733
https://digitalcommons.calpoly.edu/cgi/viewcontent.cgi?article=2961&context=theses
id ndltd-CALPOLY-oai-digitalcommons.calpoly.edu-theses-2961
record_format oai_dc
spelling ndltd-CALPOLY-oai-digitalcommons.calpoly.edu-theses-29612021-08-20T05:02:19Z Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels Ritter, David M Smilkstein, Tina, Dr. This thesis combines Keysight’s SystemVue software with a Vector Signal Analyzer (VSA) and Vector Signal Generator (VSG) to test receiver equalization schemes over physical channels. The testing setup, “Equalization Verification,” is intended to be able to evaluate any equalization scheme over any physical channel, and a decision-directed feed-forward LMS equalizer is used as an example. The decision-directed feed-forward LMS equalizer is shown to decrease the BER from 10-2 to 10-3 (average of all trials) over a CAT7 and CAT6A cable, both simulated and physical, for 1GHz and 2GHz carrier, and 80MHz data rate. A wireless channel, 2.4GHz Dipole Antenna, is also tested to show that the addition of the equalization scheme decreases BER from 10-5 to less than 10-5. Then the simulation and equalization parameters (LMS step size, PRBS, etc.) are changed to further verify the equalization scheme. The simulated channel BER results do not always match the physical channel BER results, but the equalization scheme does decrease BER for both wired and wireless channels. Then transistor-based equalization model is created using both HDL SystemVue components and blocks easily implemented by transistors. The model is then verified using HDL, Spice, and SystemVue simulation. Overall this thesis accomplishes its goal of creating a testing setup, Equalization Verification, to show that adding a given simulated equalization scheme in SystemVue can improve the quality of the link, by decreasing BER by at least an order of magnitude, over a specific physical channel. 2017-06-01T07:00:00Z text application/pdf https://digitalcommons.calpoly.edu/theses/1733 https://digitalcommons.calpoly.edu/cgi/viewcontent.cgi?article=2961&context=theses Master's Theses DigitalCommons@CalPoly Equalization Decision-directed SystemVue Vector Signal Analyzer Vector Signal Generator CAT7 Signal Processing Systems and Communications
collection NDLTD
format Others
sources NDLTD
topic Equalization
Decision-directed
SystemVue
Vector Signal Analyzer
Vector Signal Generator
CAT7
Signal Processing
Systems and Communications
spellingShingle Equalization
Decision-directed
SystemVue
Vector Signal Analyzer
Vector Signal Generator
CAT7
Signal Processing
Systems and Communications
Ritter, David M
Smilkstein, Tina, Dr.
Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
description This thesis combines Keysight’s SystemVue software with a Vector Signal Analyzer (VSA) and Vector Signal Generator (VSG) to test receiver equalization schemes over physical channels. The testing setup, “Equalization Verification,” is intended to be able to evaluate any equalization scheme over any physical channel, and a decision-directed feed-forward LMS equalizer is used as an example. The decision-directed feed-forward LMS equalizer is shown to decrease the BER from 10-2 to 10-3 (average of all trials) over a CAT7 and CAT6A cable, both simulated and physical, for 1GHz and 2GHz carrier, and 80MHz data rate. A wireless channel, 2.4GHz Dipole Antenna, is also tested to show that the addition of the equalization scheme decreases BER from 10-5 to less than 10-5. Then the simulation and equalization parameters (LMS step size, PRBS, etc.) are changed to further verify the equalization scheme. The simulated channel BER results do not always match the physical channel BER results, but the equalization scheme does decrease BER for both wired and wireless channels. Then transistor-based equalization model is created using both HDL SystemVue components and blocks easily implemented by transistors. The model is then verified using HDL, Spice, and SystemVue simulation. Overall this thesis accomplishes its goal of creating a testing setup, Equalization Verification, to show that adding a given simulated equalization scheme in SystemVue can improve the quality of the link, by decreasing BER by at least an order of magnitude, over a specific physical channel.
author Ritter, David M
Smilkstein, Tina, Dr.
author_facet Ritter, David M
Smilkstein, Tina, Dr.
author_sort Ritter, David M
title Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
title_short Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
title_full Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
title_fullStr Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
title_full_unstemmed Verification of Receiver Equalization by Integrating Dataflow Simulation and Physical Channels
title_sort verification of receiver equalization by integrating dataflow simulation and physical channels
publisher DigitalCommons@CalPoly
publishDate 2017
url https://digitalcommons.calpoly.edu/theses/1733
https://digitalcommons.calpoly.edu/cgi/viewcontent.cgi?article=2961&context=theses
work_keys_str_mv AT ritterdavidm verificationofreceiverequalizationbyintegratingdataflowsimulationandphysicalchannels
AT smilksteintinadr verificationofreceiverequalizationbyintegratingdataflowsimulationandphysicalchannels
_version_ 1719460457514795008