| Summary: | Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.
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