Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip

Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time p...

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Bibliographic Details
Main Author:	Isaacson, Spencer W.
Format:	Others
Published:	BYU ScholarsArchive 2007
Subjects:	FPGA hardware RTOS real-time fast context switch register bank task task-resource matrix embedded computer architecture hardware scheduler task switch hardware assisted RTOS Electrical and Computer Engineering
Online Access:	https://scholarsarchive.byu.edu/etd/971 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd

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spelling	ndltd-BGMYU2-oai-scholarsarchive.byu.edu-etd-19702019-05-16T03:14:17Z Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip Isaacson, Spencer W. Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor communication and synchronization. 2007-07-12T07:00:00Z text application/pdf https://scholarsarchive.byu.edu/etd/971 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd http://lib.byu.edu/about/copyright/ All Theses and Dissertations BYU ScholarsArchive FPGA hardware RTOS real-time fast context switch register bank task task-resource matrix embedded computer architecture hardware scheduler task switch hardware assisted RTOS Electrical and Computer Engineering
collection	NDLTD
format	Others
sources	NDLTD
topic	FPGA hardware RTOS real-time fast context switch register bank task task-resource matrix embedded computer architecture hardware scheduler task switch hardware assisted RTOS Electrical and Computer Engineering
spellingShingle	FPGA hardware RTOS real-time fast context switch register bank task task-resource matrix embedded computer architecture hardware scheduler task switch hardware assisted RTOS Electrical and Computer Engineering Isaacson, Spencer W. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
description	Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor communication and synchronization.
author	Isaacson, Spencer W.
author_facet	Isaacson, Spencer W.
author_sort	Isaacson, Spencer W.
title	Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
title_short	Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
title_full	Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
title_fullStr	Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
title_full_unstemmed	Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip
title_sort	hardware support for a configurable architecture for real-time embedded systems on a programmable chip
publisher	BYU ScholarsArchive
publishDate	2007
url	https://scholarsarchive.byu.edu/etd/971 https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd
work_keys_str_mv	AT isaacsonspencerw hardwaresupportforaconfigurablearchitectureforrealtimeembeddedsystemsonaprogrammablechip
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Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip

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