Hardware Synthesis of Synchronous Data Flow Models

Hardware Synthesis of Synchronous Data Flow Models

Synchronous Dataflow (SDF) graphs are a convenient way to represent many signal processing and dataflow operations. Nodes within SDF graphs represent computation while arcs represent dependencies between nodes. Using a graph representation, SDF graphs formally specify a dataflow algorithm without an...

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Bibliographic Details
Main Author: Koecher, Matthew R.
Format: Others
Published: BYU ScholarsArchive 2004
Subjects:
hardware synthesis
ptolemy
java
synchronous dataflow
SDF
abstract circuit graph
ACG
Electrical and Computer Engineering
Online Access:https://scholarsarchive.byu.edu/etd/20
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1019&context=etd

Internet

https://scholarsarchive.byu.edu/etd/20
https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1019&context=etd

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