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01623 am a22002653u 4500 |
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74123 |
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|a dc
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|a Vitale, Steven A.
|e author
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|a Lincoln Laboratory
|e contributor
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|a Vitale, Steven A.
|e contributor
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|a Wyatt, Peter W.
|e contributor
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|a Checka, Nisha
|e contributor
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|a Kedzierski, Jakub T.
|e contributor
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|a Keast, Craig L.
|e contributor
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|a Wyatt, Peter W.
|e author
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|a Checka, Nisha
|e author
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|a Kedzierski, Jakub T.
|e author
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|a Keast, Craig L.
|e author
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|a FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics
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|b Institute of Electrical and Electronics Engineers (IEEE),
|c 2012-10-18T20:41:30Z.
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| 856 |
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|z Get fulltext
|u http://hdl.handle.net/1721.1/74123
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|a Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.
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|a en_US
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|a Article
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|t Proceedings of the IEEE
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