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|a Majzoobi, Mehrdad
|e author
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|a Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory
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|a Majzoobi, Mehrdad
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|a Koushanfar, Farinaz
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|a Koushanfar, Farinaz
|e author
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|a Devadas, Srinivas
|e author
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|a FPGA-based true random number generation using circuit metastability with adaptive feedback control
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|b Springer Berlin / Heidelberg,
|c 2012-10-10T18:14:57Z.
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|z Get fulltext
|u http://hdl.handle.net/1721.1/73860
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|a 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings
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|a The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.
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|a en_US
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|a Article
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|t Cryptographic Hardware and Embedded Systems - CHES 2011
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