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71960 |
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|a dc
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|a Gogineni, Usha
|e author
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|a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
|e contributor
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|a del Alamo, Jesus A.
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|a Gogineni, Usha
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|a del Alamo, Jesus A.
|e contributor
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|a del Alamo, Jesus A.
|e author
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|a Valdes-Garcia, Alberto
|e author
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|a Analytical model for RF power performance of deeply scaled CMOS devices
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|b Institute of Electrical and Electronics Engineers (IEEE),
|c 2012-08-02T18:45:26Z.
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|z Get fulltext
|u http://hdl.handle.net/1721.1/71960
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|a This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.
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|a Semiconductor Research Corporation. (Grant Number 2007-HJ-1661)
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|a en_US
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|a Article
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|t 2011 IEEE Radio Frequency Integrated Circuits Symposium
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