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|a Hashemi, Pouya
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|a Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
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|a Massachusetts Institute of Technology. Microsystems Technology Laboratories
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|a Hoyt, Judy L.
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|a Hashemi, Pouya
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|a Teherani, James T.
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|a Hoyt, Judy L.
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|a Teherani, James T.
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|a Hoyt, Judy L.
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|a Investigation of hole mobility in gate-all-around Si nanowire p-MOSFETs with high-k/metal-gate: Effects of hydrogen thermal annealing and nanowire shape
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|b Institute of Electrical and Electronics Engineers (IEEE),
|c 2012-07-30T12:40:12Z.
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|z Get fulltext
|u http://hdl.handle.net/1721.1/71882
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|a A detailed study of hole mobility is presented for gate-all-around Si nanowire p-MOSFETs with conformal high-κ/MG and various high-temperature hydrogen annealing processes. Hole mobility enhancement relative to planar SOI devices and universal (100) is observed for 15 nm-diameter circular Si nanowires, due to an optimized anneal process which smoothes and reshapes the suspended nanowires. Increasing hole mobility is experimentally observed with decreasing nanowire width down to 12 nm. The measured inversion capacitance-voltage characteristics are in excellent agreement with quantum mechanical simulations. In addition, a method to extract areal inversion charge density in Si nanowires is introduced and its impact on the mobility of Si nanowires with various shapes is explored.
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|a Semiconductor Research Corporation. Center for Materials, Structures and Devices
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|a en_US
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|a Article
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|t 2010 IEEE International Electron Devices Meeting (IEDM)
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