A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time Delta Sigma ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 mu m CMOS

• Main Authors: Park, Matthew (Contributor), Perrott, Michael H. (Contributor)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor)
• Format: Article
• Language: English
• Published: Institute of Electrical and Electronics Engineers, 2010-05-11T14:20:39Z.
• Subjects: Article
• Online Access: Get fulltext

 The use of a VCO-based integrator and quantizer within a continuous-time (CT) \Delta \Sigma analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 \mum CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm[superscript 2] demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.