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137180.2 |
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|a Yang, Tien-Ju
|e author
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|a Massachusetts Institute of Technology. Microsystems Technology Laboratories
|e contributor
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|a Sze, Vivienne
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|a Design Considerations for Efficient Deep Neural Networks on Processing-in-Memory Accelerators
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|b Institute of Electrical and Electronics Engineers (IEEE),
|c 2021-11-15T20:37:23Z.
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|z Get fulltext
|u https://hdl.handle.net/1721.1/137180.2
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|a © 2019 IEEE. This paper describes various design considerations for deep neural networks that enable them to operate efficiently and accurately on processing-in-memory accelerators. We highlight important properties of these accelerators and the resulting design considerations using experiments conducted on various state-of-the- art deep neural networks with the large-scale ImageNet dataset.
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|a NSF (Grant E2CDA 1639921)
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|a en
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|a Article
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|t Technical Digest - International Electron Devices Meeting, IEDM
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