Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling
Graph processing is increasingly bottlenecked by main memory accesses. On-chip caches are of little help because the irregular structure of graphs causes seemingly random memory references. However, most real-world graphs offer significant potential locality-it is just hard to predict ahead of time....
| Main Authors: | , , , , |
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| Other Authors: | , |
| Format: | Article |
| Language: | English |
| Published: |
Institute of Electrical and Electronics Engineers (IEEE),
2020-03-24T18:50:57Z.
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| Subjects: | |
| Online Access: | Get fulltext |