Scalable multi-access flash store for big data analytics

• Main Authors: Jun, Sang-Woo (Author), Liu, Ming (Author), Fleming, Kermin Elliott (Author), Arvind, Arvind (Author)
• Other Authors: Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science (Contributor), Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory (Contributor), Massachusetts Institute of Technology. Department of Materials Science and Engineering (Contributor)
• Format: Article
• Language: English
• Published: Association for Computing Machinery (ACM), 2019-06-28T15:45:00Z.
• Subjects: Article
• Online Access: Get fulltext

 For many "Big Data" applications, the limiting factor in performance is often the transportation of large amount of data from hard disks to where it can be processed, i.e. DRAM. In this paper we examine an architecture for a scalable distributed flash store which aims to overcome this limitation in two ways. First, the architecture provides a highperformance, high-capacity, scalable random-access storage. It achieves high-throughput by sharing large numbers of flash chips across a low-latency, chip-to-chip backplane network managed by the flash controllers. The additional latency for remote data access via this network is negligible as compared to flash access time. Second, it permits some computation near the data via a FPGA-based programmable flash controller. The controller is located in the datapath between the storage and the host, and provides hardware acceleration for applications without any additional latency. We have constructed a small-scale prototype whose network bandwidth scales directly with the number of nodes, and where average latency for user software to access flash store is less than 70?s, including 3.5?s of network overhead.