Asymmetrical nine-level inverter topology with reduce power semicondutor devices
In this paper a new single-phase multilevel inverter topology is presented. Proposed topology is capable of producing nine-level output voltage with reduce device counts. It can be achieved by arranging available switches and dc sources in a fashion such that the maximum combination of addition and...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Universitas Ahmad Dahlan,
2018-02.
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| Subjects: | |
| Online Access: | Get fulltext |