| 520 |
|
|
|a As semiconductor technology advances further into nanometer regime, integrated circuit testing and validation continues to play a very important role to ensure high quality product. Conventionally, test patterns are generated from a gate level netlist using test generation tool. However, as the digital design increases in complexity, the gate level test generation process becomes more complicated and time consuming. As an extended alternative to this, functional fault model like micro operation fault model was introduced. However, in order to implement this, proper automation is necessary while minimizing intensive manual labor. Unfortunately, currently there is only proprietary version of automation available. In this project, an automated platform to generate test pattern using micro operation fault model was built using Perl programming language. The methodology involves conversion of behavioral model of design under test into extended finite state machine. This is followed by micro operation fault detection, fault activation and fault propagation with all the corresponding constraint sequences captured and converted into constraint model using SystemVerilog, a hardware description language. These models of fault free and intended faulty circuit were fed into a constraint solver tool, VCS by Synopsys to generate the test pattern. For verification purpose, these test patterns were validated by simulating the circuit using Altera Quartus II tool. The result of this project shows that reasonable fault coverage was achieved using this methodology.
|
