| Summary: | With the evolution of Very Large Scale Integration (VLSI) fabrication technology, circuit size has grown and line width has decreased. In effect, the transistor transit time and the time to drive signal lines across chips have also decreased. Thus, interconnections have become the dominating factor in determining circuit performance and reliability in the design of a VLSI circuit. Clock distribution network, which is one of the biggest and most important nets in any synchronous VLSI chip, is sensitive to these variations. The increased line resistance is one of the primary reasons for the increasing significance of clock distribution networks on synchronous performance. Furthermore, failing to control the clock skew can also severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may be latched by register. This thesis proposes a Computer Aided-Design (CAD) software module for useful-skew tree synthesis in deep-sub-micron VLSI design. Building the proposed CAD software module involves the implementations of the abstract topology generation algorithm, skew constraints scheduling algorithm and clock tree construction algorithm. Due to the lack of availability of circuit data and necessary software tools, we introduced a different test methodology to test the reliability of the proposed CAD software module. Two different test data have been used to verify the functionality of the CAD software module. Tests on the random input data show that our CAD software module successfully synthesizes clock trees that satisfy the entire clock skew constraints, and at the same time, achieve a shorter wire-length. Tests on benchmark circuit's data show that our CAD software module successfully synthesizes clock trees that not only satisfy the skew constraint value, but also further reduced the computed applicable clock period of the circuit.
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