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|a Semiconductor memories are widely considered as one of the most important types of microelectronic components in the modern digital systems. The growing need for storage in computer, communications and consumer applications is driving the continuous innovation of various semiconductor memory technologies. Memories are more vulnerable to physical defects than logic circuits because of the former have high density and more complicated processing steps. Hence, investing in fault modelling and simulation, test algorithm development and evaluation, design-fortestability (DFT), built-in self-test (BIST) and diagnostics has been considered as one of the key factors in producing successful memory as well as system-on-chip (SoC) products. Tools for fault model evaluation and test algorithm generation are fundamental for tackling the above issues efficiently. March test algorithms are developed to detect these faults. Majority of the published march tests have been manually generated. Unfortunately, the continuous evolution of the memory technology introduces new classes of faults. This makes the task of handwriting test algorithms harder and as well the task of analyzing these algorithms becomes more complicated. Doing this manually does not always lead to optimal results. Therefore, it is becoming evident that it is more feasible to perform algorithm generation and fault simulation in an automated way. In this thesis, we develop a program to generate March test automatically. The focus is to ensure that the generator is able to product March tests that cover most typical faults in memories. Each March test generated is carefully analysed to ensure that it meets the required fault coverage. Prior to this, the characteristics of each memory fault are studied so that fault behaviour of the particular is correctly represented in form of fault primitive. As a result, the generator developed in this project is able to correctly generate March test with full coverage of the target fault.
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