Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

• Main Authors: B. Kalagadda, N. Muthyala, K.K. Korlapati
• Format: Article
• Language: English
• Published: Sultan Qaboos University 2017-03-01
• Series: The Journal of Engineering Research
• Subjects: sub-threshold leakage, stack, sleep, sleepy keeper, static power.
• Online Access: https://journals.squ.edu.om/index.php/tjer/article/view/188

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.