Design and Analysis of Three-Stage Amplifier for Driving pF-to-nF Capacitive Load Based on Local <i>Q</i>-Factor Control and Cascode Miller Compensation Techniques

• Main Authors: Qi Cheng, Weimin Li, Xian Tang, Jianping Guo
• Format: Article
• Language: English
• Published: MDPI AG 2019-05-01
• Series: Electronics
• Subjects: three-stage CMOS amplifiers; cascode miller compensation; local <i>Q</i>-factor control; pole-zero cancellation; wide drivability range
• Online Access: https://www.mdpi.com/2079-9292/8/5/572

This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local <i>Q</i>-factor control (LQC) loop is introduced to alter the <i>Q</i>-factor adaptively when loading capacitance <i>C_L</i> varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the <i>Q</i>-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-&#181;m CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375&#215; drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3&#176; phase margin (PM), while consuming 24.0-&#181;W quiescent power at 1.0-V nominal supply voltage.