EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS

A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minim...

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Bibliographic Details
Main Authors: N. A. Avdeev, P. N. Bibilo
Format: Article
Language:Russian
Published: The United Institute of Informatics Problems of the National Academy of Sciences of Belarus 2016-09-01
Series:Informatika
Online Access:https://inf.grid.by/jour/article/view/23
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spelling doaj-fad5cb1d1d504b6f94d313c2aa628dd02021-07-28T21:07:21ZrusThe United Institute of Informatics Problems of the National Academy of Sciences of Belarus Informatika1816-03012016-09-0102859322EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITSN. A. Avdeev0P. N. Bibilo1Объединенный институт проблем информатики НАН БеларусиОбъединенный институт проблем информатики НАН БеларусиA formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.https://inf.grid.by/jour/article/view/23
collection DOAJ
language Russian
format Article
sources DOAJ
author N. A. Avdeev
P. N. Bibilo
spellingShingle N. A. Avdeev
P. N. Bibilo
EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
Informatika
author_facet N. A. Avdeev
P. N. Bibilo
author_sort N. A. Avdeev
title EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
title_short EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
title_full EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
title_fullStr EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
title_full_unstemmed EMPLOYING COMPLEXITY ESTIMATES OF BINARY DECISION DIAGRAMS IN THE SYNTHESIS OF LOGICAL CIRCUITS
title_sort employing complexity estimates of binary decision diagrams in the synthesis of logical circuits
publisher The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
series Informatika
issn 1816-0301
publishDate 2016-09-01
description A formula is suggested to evaluate the area of a logical circuit that is built in a given library of logical elements according to the BDD (Binary Decision Diagram) representation of a system of Boolean functions. The experimental results of synthesis of combinational logical circuits from the minimized BDD representations in the design library of custom CMOS VLSI circuits are described.
url https://inf.grid.by/jour/article/view/23
work_keys_str_mv AT naavdeev employingcomplexityestimatesofbinarydecisiondiagramsinthesynthesisoflogicalcircuits
AT pnbibilo employingcomplexityestimatesofbinarydecisiondiagramsinthesynthesisoflogicalcircuits
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