Performance analysis of massively parallel embedded hardware architectures for retinal image processing

• Main Authors: Osorio Roberto, Nieto Alejandro, Brea Victor, Vilariño David
• Format: Article
• Language: English
• Published: SpringerOpen 2011-01-01
• Series: EURASIP Journal on Image and Video Processing
• Online Access: http://jivp.eurasipjournals.com/content/2011/1/10

<p>Abstract</p> <p>This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).</p>