| Summary: | In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (<i>T<sub>ILD</sub></i>) and gate channel length (<i>L<sub>g</sub></i>) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as <i>T<sub>ILD</sub></i> decreases and they increase as <i>L<sub>g</sub></i> increases, and thus there is a strong coupling in M3INV at the range of <i>T<sub>ILD</sub></i> ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same <i>T<sub>ILD</sub></i> and <i>L<sub>g</sub></i>. The switching threshold voltage (<i>V<sub>m</sub></i>) and noise margins (<i>NM</i>s) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the <i>V<sub>m</sub></i> variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of <i>V<sub>m</sub></i>, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.
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