LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the...

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Bibliographic Details
Main Authors: Chen-Hung Lin, Chen-Xuan Wang, Cheng-Kai Lu
Format: Article
Language:English
Published: MDPI AG 2021-08-01
Series:Electronics
Subjects:
error correction code
low-density parity-check code
min-sum algorithm
ASIC implementation
Online Access:https://www.mdpi.com/2079-9292/10/16/2010

Internet

https://www.mdpi.com/2079-9292/10/16/2010

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