Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL

Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL

This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency. The frequency synthesizer requirement comes from our complex radio transmission system...

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Bibliographic Details
Main Authors: Daniel Kekrt, Milos Klima, Radek Podgorny, Jan Zavrtalek
Format: Article
Language:English
Published: VSB-Technical University of Ostrava 2012-01-01
Series:Advances in Electrical and Electronic Engineering
Subjects:
direct frequency synthesis
vhdl
fpga
memory efficiency
logic synthesis.
Online Access:http://advances.utc.sk/index.php/AEEE/article/view/531
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spelling doaj-f5574df96751499c9fa7660b1413b09d2021-10-11T08:03:02ZengVSB-Technical University of OstravaAdvances in Electrical and Electronic Engineering1336-13761804-31192012-01-01102818810.15598/aeee.v10i2.531522Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDLDaniel KekrtMilos KlimaRadek PodgornyJan ZavrtalekThis article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency. The frequency synthesizer requirement comes from our complex radio transmission system design. The research activity has been focused on finding an optimal balance between simplicity, speed and memory consumption. The modelling was done in MATLAB environment in floating-point and fixed-point arithmetic, and the actual design was implemented and synthesized using the Xilinx ISE suite. The output has been connected to our customized radio front-end built on the Texas Instruments TRF2443 chip. The front-end output signal has been captured and compared with simulation results.http://advances.utc.sk/index.php/AEEE/article/view/531direct frequency synthesisvhdlfpgamemory efficiencylogic synthesis.
collection DOAJ
language English
format Article
sources DOAJ
author Daniel Kekrt
Milos Klima
Radek Podgorny
Jan Zavrtalek
spellingShingle Daniel Kekrt
Milos Klima
Radek Podgorny
Jan Zavrtalek
Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
Advances in Electrical and Electronic Engineering
direct frequency synthesis
vhdl
fpga
memory efficiency
logic synthesis.
author_facet Daniel Kekrt
Milos Klima
Radek Podgorny
Jan Zavrtalek
author_sort Daniel Kekrt
title Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
title_short Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
title_full Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
title_fullStr Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
title_full_unstemmed Implementation of Different Variants of Table-Based Frequency Synthesizers with Quadrature Output in VHDL
title_sort implementation of different variants of table-based frequency synthesizers with quadrature output in vhdl
publisher VSB-Technical University of Ostrava
series Advances in Electrical and Electronic Engineering
issn 1336-1376
1804-3119
publishDate 2012-01-01
description This article describes the modelling and implementation of two different variants of direct frequency synthesizer, and evaluation of the performance of the finished design, in terms of memory and speed efficiency. The frequency synthesizer requirement comes from our complex radio transmission system design. The research activity has been focused on finding an optimal balance between simplicity, speed and memory consumption. The modelling was done in MATLAB environment in floating-point and fixed-point arithmetic, and the actual design was implemented and synthesized using the Xilinx ISE suite. The output has been connected to our customized radio front-end built on the Texas Instruments TRF2443 chip. The front-end output signal has been captured and compared with simulation results.
topic direct frequency synthesis
vhdl
fpga
memory efficiency
logic synthesis.
url http://advances.utc.sk/index.php/AEEE/article/view/531
work_keys_str_mv AT danielkekrt implementationofdifferentvariantsoftablebasedfrequencysynthesizerswithquadratureoutputinvhdl
AT milosklima implementationofdifferentvariantsoftablebasedfrequencysynthesizerswithquadratureoutputinvhdl
AT radekpodgorny implementationofdifferentvariantsoftablebasedfrequencysynthesizerswithquadratureoutputinvhdl
AT janzavrtalek implementationofdifferentvariantsoftablebasedfrequencysynthesizerswithquadratureoutputinvhdl
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