A New and Efficient Scheme for Improving the Digitized Chaotic Systems From Dynamical Degradation

• Main Authors: Lahcene Merah, Pascal Lorenz, Ali-Pacha Adda
• Format: Article
• Language: English
• Published: IEEE 2021-01-01
• Series: IEEE Access
• Subjects: PRNG; cryptography; statistical properties; transient-length; cycle-length; FPGA
• Online Access: https://ieeexplore.ieee.org/document/9456889/

Chaotic systems are good alternatives for designing PRNGs, but however, their implementation using finite arithmetic precision leads to serious degradation in their dynamics. This paper aims to treat this issue, in which we propose an efficient scheme to surmount the occurring dynamical degradation as much as possible, taking into account the factor of the implementation cost. The proposed scheme is based on the principle of saving portions of the history of the chaotic sequence and compares on the fly the chaotic sequence with the saved samples. If any equality is detected, the proposed scheme will perturb the chaotic orbit to avoid falling on a cycle. The advantage of the proposed scheme is that it does not need any external source for the perturbation, it has a self-perturbation mechanism. The proposed scheme has been evaluated using the Logistic map implemented with low arithmetic precision, and it has been evaluated using many mathematical and statistical tools. The obtained results using the modified map are quite better than the original map. In addition to the good statistical properties (<inline-formula> <tex-math notation="LaTeX">$SampEn \simeq 1.7, ApEn \simeq 0.8, PE~\simeq 0.97$ </tex-math></inline-formula>, NIST success rate 75&#x0025;, and DieHard success rate 57.89&#x0025;), the new obtained cycle-length cannot be detected, usually, this result can be achieved only by using higher arithmetic precision which is expensive in terms of the implementation cost. The proposed scheme has also compared with some proposals in which it provided the best results in terms of the statistical properties, unpredictability, and implementation cost using FPGA.