OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Finite difference time domain (FDTD) method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown...

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Main Authors: Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
Format: Article
Language:English
Published: Hindawi Limited 2017-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2017/6817674
id doaj-f32d37ec03ff456d8f16f99f9c3ce5c3
record_format Article
spelling doaj-f32d37ec03ff456d8f16f99f9c3ce5c32020-11-24T22:09:28ZengHindawi LimitedInternational Journal of Reconfigurable Computing1687-71951687-72092017-01-01201710.1155/2017/68176746817674OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary ConditionsHasitha Muthumala Waidyasooriya0Tsukasa Endo1Masanori Hariyama2Yasuo Ohtera3Graduate School of Information Sciences, Tohoku University, Aoba 6-3-09, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, JapanGraduate School of Information Sciences, Tohoku University, Aoba 6-3-09, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, JapanGraduate School of Information Sciences, Tohoku University, Aoba 6-3-09, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, JapanGraduate School of Information Sciences, Tohoku University, Aoba 6-3-05, Aramaki-Aza-Aoba, Sendai, Miyagi 980-8579, JapanFinite difference time domain (FDTD) method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language). As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.http://dx.doi.org/10.1155/2017/6817674
collection DOAJ
language English
format Article
sources DOAJ
author Hasitha Muthumala Waidyasooriya
Tsukasa Endo
Masanori Hariyama
Yasuo Ohtera
spellingShingle Hasitha Muthumala Waidyasooriya
Tsukasa Endo
Masanori Hariyama
Yasuo Ohtera
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
International Journal of Reconfigurable Computing
author_facet Hasitha Muthumala Waidyasooriya
Tsukasa Endo
Masanori Hariyama
Yasuo Ohtera
author_sort Hasitha Muthumala Waidyasooriya
title OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
title_short OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
title_full OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
title_fullStr OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
title_full_unstemmed OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
title_sort opencl-based fpga accelerator for 3d fdtd with periodic and absorbing boundary conditions
publisher Hindawi Limited
series International Journal of Reconfigurable Computing
issn 1687-7195
1687-7209
publishDate 2017-01-01
description Finite difference time domain (FDTD) method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language). As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.
url http://dx.doi.org/10.1155/2017/6817674
work_keys_str_mv AT hasithamuthumalawaidyasooriya openclbasedfpgaacceleratorfor3dfdtdwithperiodicandabsorbingboundaryconditions
AT tsukasaendo openclbasedfpgaacceleratorfor3dfdtdwithperiodicandabsorbingboundaryconditions
AT masanorihariyama openclbasedfpgaacceleratorfor3dfdtdwithperiodicandabsorbingboundaryconditions
AT yasuoohtera openclbasedfpgaacceleratorfor3dfdtdwithperiodicandabsorbingboundaryconditions
_version_ 1725811635423019008