Design and Implementation of an On-Chip Low-Power and High-Flexibility System for Data Acquisition and Processing of an Inertial Measurement Unit

• Main Authors: Zhenyi Gao, Bin Zhou, Yang Li, Lei Yang, Xiang Li, Qi Wei, Hongyang Chu, Rong Zhang
• Format: Article
• Language: English
• Published: MDPI AG 2020-01-01
• Series: Sensors
• Subjects: imu; signal processing; soc; low power; miniaturization
• Online Access: https://www.mdpi.com/1424-8220/20/2/462

For signal processing of a Micro-Electro-Mechanical System (MEMS) Inertial Measurement Unit (IMU), a digital-analog hybrid system-on-chip (SoC) with small area and low power consumption was designed and implemented in this paper. To increase the flexibility of the processing circuit, the designed SoC integrates a low-power processor and supports three startup or debugging modes for different application scenarios. An application-specific computing module and communication interface are designed in the circuit to meet the requirements of IMU signal processing. The configurable clock allows users to dynamically balance computing speed and power consumption in their applications. The chip was taped out under SMIC 180 nm CMOS technology and tested for performance. The results show that the chip&#8217;s maximum running frequency is 105 MHz. The total area is 33.94 <inline-formula> <math display="inline"> <semantics> <mrow> <msup> <mrow> <mrow> <mi>mm</mi> </mrow> </mrow> <mn>2</mn> </msup> </mrow> </semantics> </math> </inline-formula>. The dynamic and static power consumption are 0.65 mW/MHz and 0.30 mW/MHz, respectively. When the system clock is 25 MHz, the dynamic and static power consumption of the chip is 76 mW and 66 mW, and the dynamic and static power consumption of the FPGA level are 634 mW and 520 mW. The results verify the superiority of the application specific integrated circuit (ASIC) solution in terms of integration and low power consumption.