Optimization of Deep Neural Networks Using SoCs with OpenCL

• Main Authors: Rafael Gadea-Gironés, Ricardo Colom-Palero, Vicente Herrero-Bosch
• Format: Article
• Language: English
• Published: MDPI AG 2018-04-01
• Series: Sensors
• Subjects: evolutionary computation; embedded system; FPGA; deep neural networks; OpenCL; SoC
• Online Access: http://www.mdpi.com/1424-8220/18/5/1384

In the optimization of deep neural networks (DNNs) via evolutionary algorithms (EAs) and the implementation of the training necessary for the creation of the objective function, there is often a trade-off between efficiency and flexibility. Pure software solutions implemented on general-purpose processors tend to be slow because they do not take advantage of the inherent parallelism of these devices, whereas hardware realizations based on heterogeneous platforms (combining central processing units (CPUs), graphics processing units (GPUs) and/or field-programmable gate arrays (FPGAs)) are designed based on different solutions using methodologies supported by different languages and using very different implementation criteria. This paper first presents a study that demonstrates the need for a heterogeneous (CPU-GPU-FPGA) platform to accelerate the optimization of artificial neural networks (ANNs) using genetic algorithms. Second, the paper presents implementations of the calculations related to the individuals evaluated in such an algorithm on different (CPU- and FPGA-based) platforms, but with the same source files written in OpenCL. The implementation of individuals on remote, low-cost FPGA systems on a chip (SoCs) is found to enable the achievement of good efficiency in terms of performance per watt.