A new Dual-Vt 4T SRAM bitcell design
Reducing the memory bit cell area by reducing the number of transistors is a relatively straightforward solution to achieving a high density SRAM design. In the design of critical SRAM cells, the stability characteristics exhibited by different operating states are important criteria for judging the...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-11-01
|
| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000093342 |