Design and Analysis of a New Carbon Nanotube Full Adder Cell
A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube te...
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2011-01-01
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Series: | Journal of Nanomaterials |
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doaj-f0d5b2e297384315867055b28af3f45c2020-11-24T23:58:11ZengHindawi LimitedJournal of Nanomaterials1687-41101687-41292011-01-01201110.1155/2011/906237906237Design and Analysis of a New Carbon Nanotube Full Adder CellM. H. Ghadiry0Asrulnizam Abd Manaf1M. T. Ahmadi2Hatef Sadeghi3M. Nadi Senejani4School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 11800 Penang, MalaysiaSchool of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 11800 Penang, MalaysiaFaculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, MalaysiaFaculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, MalaysiaDepartment of Computer Engineering, Islamic Azad University, Ashtian Branch, 39618-13347 Ashtian, IranA novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.http://dx.doi.org/10.1155/2011/906237 |
collection |
DOAJ |
language |
English |
format |
Article |
sources |
DOAJ |
author |
M. H. Ghadiry Asrulnizam Abd Manaf M. T. Ahmadi Hatef Sadeghi M. Nadi Senejani |
spellingShingle |
M. H. Ghadiry Asrulnizam Abd Manaf M. T. Ahmadi Hatef Sadeghi M. Nadi Senejani Design and Analysis of a New Carbon Nanotube Full Adder Cell Journal of Nanomaterials |
author_facet |
M. H. Ghadiry Asrulnizam Abd Manaf M. T. Ahmadi Hatef Sadeghi M. Nadi Senejani |
author_sort |
M. H. Ghadiry |
title |
Design and Analysis of a New Carbon Nanotube Full Adder Cell |
title_short |
Design and Analysis of a New Carbon Nanotube Full Adder Cell |
title_full |
Design and Analysis of a New Carbon Nanotube Full Adder Cell |
title_fullStr |
Design and Analysis of a New Carbon Nanotube Full Adder Cell |
title_full_unstemmed |
Design and Analysis of a New Carbon Nanotube Full Adder Cell |
title_sort |
design and analysis of a new carbon nanotube full adder cell |
publisher |
Hindawi Limited |
series |
Journal of Nanomaterials |
issn |
1687-4110 1687-4129 |
publishDate |
2011-01-01 |
description |
A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications. |
url |
http://dx.doi.org/10.1155/2011/906237 |
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