Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly

Fluidic self-assembly is a versatile on-chip integration method. In this scheme, a large number of semiconductor microchips are spontaneously deposited onto a host chip. The host chip typically comprises a Si substrate with an array of pockets at the designated microchip placement sites. In this stu...

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Main Authors: Yutaka Fujita, Shoji Ishihara, Yuki Nakashima, Kosuke Nishigaya, Katsuaki Tanabe
Format: Article
Language:English
Published: MDPI AG 2021-02-01
Series:Applied Mechanics
Subjects:
Online Access:https://www.mdpi.com/2673-3161/2/1/2
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spelling doaj-f0bc864adb44444682025acdf1b3072c2021-02-09T00:06:06ZengMDPI AGApplied Mechanics2673-31612021-02-0122162410.3390/applmech2010002Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-AssemblyYutaka Fujita0Shoji Ishihara1Yuki Nakashima2Kosuke Nishigaya3Katsuaki Tanabe4Department of Chemical Engineering, Kyoto University, Nishikyo, Kyoto 615-8510, JapanDepartment of Chemical Engineering, Kyoto University, Nishikyo, Kyoto 615-8510, JapanDepartment of Chemical Engineering, Kyoto University, Nishikyo, Kyoto 615-8510, JapanDepartment of Chemical Engineering, Kyoto University, Nishikyo, Kyoto 615-8510, JapanDepartment of Chemical Engineering, Kyoto University, Nishikyo, Kyoto 615-8510, JapanFluidic self-assembly is a versatile on-chip integration method. In this scheme, a large number of semiconductor microchips are spontaneously deposited onto a host chip. The host chip typically comprises a Si substrate with an array of pockets at the designated microchip placement sites. In this study, we installed an SiO<sub>2</sub> layer on the terrace region between the pockets of the host chip, to reduce the attraction with the Si microchips. By the SiO<sub>2</sub>-topped terrace scheme, we demonstrated a significant enhancement in the deposition selectivity of the Si microchips to the pocket sites, relative to the case of the conventional Si-only host chip. We theoretically explained the deposition selectivity enhancement in terms of the van der Waals interaction. Furthermore, our quantitative analysis implicated a potential applicability of the commonly used interlayer dielectrics, such as HfO<sub>2</sub>, silsesquioxanes, and allyl ethers, directly as the terrace component.https://www.mdpi.com/2673-3161/2/1/2semiconductorsiliconthin filmlayer transferself-assemblyintegration
collection DOAJ
language English
format Article
sources DOAJ
author Yutaka Fujita
Shoji Ishihara
Yuki Nakashima
Kosuke Nishigaya
Katsuaki Tanabe
spellingShingle Yutaka Fujita
Shoji Ishihara
Yuki Nakashima
Kosuke Nishigaya
Katsuaki Tanabe
Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
Applied Mechanics
semiconductor
silicon
thin film
layer transfer
self-assembly
integration
author_facet Yutaka Fujita
Shoji Ishihara
Yuki Nakashima
Kosuke Nishigaya
Katsuaki Tanabe
author_sort Yutaka Fujita
title Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
title_short Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
title_full Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
title_fullStr Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
title_full_unstemmed Selective Transfer of Si Thin-Film Microchips by SiO<sub>2</sub> Terraces on Host Chips for Fluidic Self-Assembly
title_sort selective transfer of si thin-film microchips by sio<sub>2</sub> terraces on host chips for fluidic self-assembly
publisher MDPI AG
series Applied Mechanics
issn 2673-3161
publishDate 2021-02-01
description Fluidic self-assembly is a versatile on-chip integration method. In this scheme, a large number of semiconductor microchips are spontaneously deposited onto a host chip. The host chip typically comprises a Si substrate with an array of pockets at the designated microchip placement sites. In this study, we installed an SiO<sub>2</sub> layer on the terrace region between the pockets of the host chip, to reduce the attraction with the Si microchips. By the SiO<sub>2</sub>-topped terrace scheme, we demonstrated a significant enhancement in the deposition selectivity of the Si microchips to the pocket sites, relative to the case of the conventional Si-only host chip. We theoretically explained the deposition selectivity enhancement in terms of the van der Waals interaction. Furthermore, our quantitative analysis implicated a potential applicability of the commonly used interlayer dielectrics, such as HfO<sub>2</sub>, silsesquioxanes, and allyl ethers, directly as the terrace component.
topic semiconductor
silicon
thin film
layer transfer
self-assembly
integration
url https://www.mdpi.com/2673-3161/2/1/2
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